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HW 22 - Asserting fast-back-to-back transfers in the PCI Power Mac (15-July-95)

Q Does the PCI controller in the PCI Power Macs ever assert, or is it capable of ever asserting fast-back-to-back transfers? This data transfer mode is listed under Reserve Name Registry property names in the March 9, 1995 version of Designing PCI Cards and Drivers for Power Macintosh Computers. If this transfer mode is implemented, how can it be invoked by system software for testing purposes?

A The answer to the first part of your question -- does the PCI controller in the PCI Power Macs ever assert, or is it capable of ever asserting fast-back-to-back transfers? -- is no. It can respond to fast-back-to-back transfers correctly, but it will never generate fast-back-to-back cycles.

As for the second part of your question, the property fast-back-to-back will appear in a PCI device's standard PCI properties if its PCI Configuration space Status register's fast-back-to-back-capable bit is asserted. If all devices on a PCI Bus have this property (i.e., are fast-back-to-back-capable), the system software will enable all devices fast-back-to-back-enable bits in their PCI Configuration space Command registers. That is all the property fast-back-to-back is used for.

Again, the PCI bridge chip on the PCI PowerMacs will not generate fast back to back cycles, but other masters in the system could, so your device should be able to respond to them correctly. In fact, it is a requirement from the PCI Compliance Checklist that you respond correctly to fast-back-to-back cycles. The PCI Compliance Checklist is available from the PCI SIG.

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